Parallel processors have a plurality of individual processors, all capable of cooperating on the same program. Parallel processors can be divided into Multiple Instruction Multiple Data (MIMD) and Single Instruction Multiple Data (SIMD) designs.
Multiple Instruction Multiple Data (MIMD) parallel processors have individual processing nodes characterized by fast microprocessors supported by many memory chips and a memory hierarchy. High performance inter node communications coprocessor chips provide the communications links to other microprocessors. Each processor node runs an operating system kernel, with communications at the application level being through a standardized library of message passing functions. In the MIMD parallel processor both shared and distributed memory models are supported.
Single Instruction Multiple Data (SIMD) parallel processors have a plurality of individual processor elements under the control of a single control unit and connected by an intercommunication unit. SIMD machines have an architecture that is specified by:
1. The number of processing elements in the machine.
2. The number of instructions that can be directly executed by the control unit. This includes both scalar instructions and program flow instructions.
3. The number of instructions broadcast by the control unit to all of the processor elements for parallel execution. This includes arithmetic, logic, data routing, masking, and local operations executed by each active processor element over data within the processor element.
4. The number of masking schemes, where each mask partitions the set of processor elements into enabled and disabled subsets.
5. The number of data routing functions, which specify the patterns to be set up in the interconnection network for inter-processor element communications.
SIMD processors have a large number of specialized support chips to support dozens to hundreds of fixed point data flows. Instructions come from outside the individual node, and distributed memory is supported.
Parallel processors require a complex and sophisticated intercommunication network for processor-processor and processor-memory communications. The topology of the interconnection network can be either static or dynamic. Static networks are formed of point-to-point direct connections which will not change during program execution. Dynamic networks are implemented with switched channels which can dynamically reconfigure to match the communications requirements of the programs running on the parallel processor.
Dynamic networks are particularly preferred for multi-purpose and general purpose applications, Dynamic networks can implement communications patterns based on a program demands. Dynamic networking is provided by one or more of bus systems, multistage intercommunications networks, and crossbar switch networks.
Critical to all parallel processors, and especially to dynamic networks is the packaging of the interconnection circuitry. Specifically, the interconnection must provide high speed switching, with low signal attenuation, low crosstalk, and low noise.